dts: arm: microchip: mec: Add MEC5 HAL based GIRQ information #91715
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Microchip MEC SoC's include an interrupt aggregator affecting the routing of interrupt to the ARM NVIC. IA can not be treated as a true second level interrupt controller. All interrupt sources with the exception of GPIOs and eSPI virtual wires can be routed by IA to individial NVIC inputs. Each bank of GPIOs and VWires are aggregated into a single NVIC input per bank. For the NVIC to receive the interrupt signal the respective GIRQ enable must be set. We attempted to add this informatation by encoding the DT irq property. This exeperiment failed due to how Zephyr builds the interrupt tables and MEC IA is not a true second level interrupt controller. Therefore, drivers for MEC peripherals need to GIRQ number and bit position to pass to HAL API's or if a driver is implemented in the linux style without using the full MEC HAL the GIRQ information is present in DT. Signed-off-by: Scott Worley <scott.worley@microchip.com>
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Found mistake in ps2_1 node register address. Fixed and pushed update. |
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albertofloyd
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Jul 2, 2025
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Microchip MEC SoC's include an interrupt aggregator affecting the routing of interrupt to the ARM NVIC. IA can not be treated as a true second level interrupt controller. All interrupt sources with the exception of GPIOs and eSPI virtual wires can be routed by IA to individial NVIC inputs. Each bank of GPIOs and VWires are aggregated into a single NVIC input per bank. For the NVIC to receive the interrupt signal the respective GIRQ enable must be set. We attempted to add this informatation by encoding the DT irq property. This exeperiment failed due to how Zephyr builds the interrupt tables and MEC IA is not a true second level interrupt controller. Therefore, drivers for MEC peripherals need to GIRQ number and bit position to pass to HAL API's or if a driver is implemented in the linux style without using the full MEC HAL the GIRQ information is present in DT.